<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3247384</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Fri May  2 22:15:57 2025</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2021.1 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>b16e7cee45744c23a88303fe6087cc73</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>19</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>677f9e0b228058c1a06071a4c4137f3c</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>677f9e0b228058c1a06071a4c4137f3c</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a200t</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>fbg484</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-2</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i7-13620H</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2918 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>16.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addrepositoryinfodialog_ok=2</TD>
   <TD>applyrsbmultiautomationdialog_checkbox_tree=3</TD>
   <TD>basedialog_apply=1</TD>
   <TD>basedialog_cancel=77</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_ok=83</TD>
   <TD>basereporttab_rerun=3</TD>
   <TD>cmdmsgdialog_messages=2</TD>
   <TD>cmdmsgdialog_ok=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>cmdmsgdialog_open_messages_view=1</TD>
   <TD>commandsinput_type_tcl_command_here=1</TD>
   <TD>constraintschooserpanel_add_files=7</TD>
   <TD>coretreetablepanel_core_tree_table=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>createconstraintsfilepanel_file_name=2</TD>
   <TD>createnewdiagramdialog_design_name=1</TD>
   <TD>customizecoredialog_documentation=2</TD>
   <TD>customizecoredialog_ip_location=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>exportplatformwizard_fixed_post_impl=8</TD>
   <TD>filesetpanel_file_set_panel_tree=207</TD>
   <TD>flownavigatortreepanel_flow_navigator_tree=100</TD>
   <TD>hacgcbitstringeditor_value_of_specified_parameter=12</TD>
</TR><TR ALIGN='LEFT'>   <TD>hacgcbitstringeditor_value_of_specified_parameter_manual=10</TD>
   <TD>hacgcipsymbol_show_disabled_ports=2</TD>
   <TD>hjfilechooserrecentlistpreview_recent_directories=2</TD>
   <TD>hpopuptitle_close=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>ipstatussectionpanel_ip_up_to_date=4</TD>
   <TD>ipstatussectionpanel_upgrade_selected=2</TD>
   <TD>ipstatustablepanel_ip_status_table=28</TD>
   <TD>ipstatustablepanel_more_info=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>launchrunmsgdialog_cancel_run=1</TD>
   <TD>mainmenumgr_checkpoint=36</TD>
   <TD>mainmenumgr_constraints=14</TD>
   <TD>mainmenumgr_edit=12</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_export=50</TD>
   <TD>mainmenumgr_file=78</TD>
   <TD>mainmenumgr_flow=4</TD>
   <TD>mainmenumgr_help=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_import=20</TD>
   <TD>mainmenumgr_ip=39</TD>
   <TD>mainmenumgr_open_recent_ip_location=3</TD>
   <TD>mainmenumgr_project=35</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_reports=16</TD>
   <TD>mainmenumgr_text_editor=35</TD>
   <TD>mainmenumgr_tools=12</TD>
   <TD>mainmenumgr_view=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_window=10</TD>
   <TD>mainwinmenumgr_layout=10</TD>
   <TD>modifiedconstraintswithouttargetdialog_update=1</TD>
   <TD>msgtreepanel_message_view_tree=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>netlistschematicview_show_io_ports_in_this_schematic=26</TD>
   <TD>netlistschematicview_show_nets_in_this_schematic=1</TD>
   <TD>pacommandnames_add_sources=8</TD>
   <TD>pacommandnames_auto_connect_ports=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_auto_update_hier=18</TD>
   <TD>pacommandnames_create_top_hdl=21</TD>
   <TD>pacommandnames_export_bitstream_files=4</TD>
   <TD>pacommandnames_export_hardware=20</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_generate_composite_file=28</TD>
   <TD>pacommandnames_import_ports=1</TD>
   <TD>pacommandnames_import_schematic=1</TD>
   <TD>pacommandnames_make_connection=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_print=1</TD>
   <TD>pacommandnames_project_summary=21</TD>
   <TD>pacommandnames_regenerate_layout=20</TD>
   <TD>pacommandnames_report_ip_status=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_show_product_guide=1</TD>
   <TD>pacommandnames_show_product_webpage=1</TD>
   <TD>pacommandnames_validate_rsb_design=17</TD>
   <TD>paviews_address_editor=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_project_summary=18</TD>
   <TD>paviews_schematic=11</TD>
   <TD>projecttab_reload=8</TD>
   <TD>rdicommands_custom_commands=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_delete=4</TD>
   <TD>rdicommands_properties=2</TD>
   <TD>rdicommands_settings=3</TD>
   <TD>rsbapplyautomationbar_run_block_automation=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>rsbapplyautomationbar_run_connection_automation=7</TD>
   <TD>rsbexternalinterfaceproppanels_name=5</TD>
   <TD>rsbexternalportproppanels_frequency=1</TD>
   <TD>rsbexternalportproppanels_name=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>rsbselectpinsdialog_pins_tree=6</TD>
   <TD>rungadget_show_error=1</TD>
   <TD>rungadget_show_error_and_critical_warning_messages=3</TD>
   <TD>rungadget_show_warning_and_error_messages_in_messages=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>saveprojectutils_save=6</TD>
   <TD>schematicview_regenerate=2</TD>
   <TD>selectmenu_highlight=13</TD>
   <TD>settingsdialog_project_tree=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>settingsprojectiprepositorypage_add_repository=2</TD>
   <TD>signaltablepanel_signal_table=66</TD>
   <TD>simpleoutputproductdialog_generate_output_products_immediately=23</TD>
   <TD>simpleoutputproductdialog_output_product_tree=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcmenu_ip_hierarchy=19</TD>
   <TD>srcmenu_open_selected_source_files=1</TD>
   <TD>stalemoreaction_out_of_date_details=1</TD>
   <TD>syntheticastatemonitor_cancel=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>systembuildermenu_ip_documentation=1</TD>
   <TD>systembuilderview_add_ip=10</TD>
   <TD>systembuilderview_expand_collapse=17</TD>
   <TD>systembuilderview_orientation=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>systembuilderview_pinning=43</TD>
   <TD>systemtreeview_system_tree=5</TD>
   <TD>taskbanner_close=10</TD>
   <TD>tclconsoleview_tcl_console_code_editor=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>xpg_textfield_value_of_specified_parameter=1</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsources=8</TD>
   <TD>autoconnectport=3</TD>
   <TD>closeproject=1</TD>
   <TD>createblockdesign=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>createtophdl=21</TD>
   <TD>customizersbblock=106</TD>
   <TD>editcopy=1</TD>
   <TD>editdelete=18</TD>
</TR><TR ALIGN='LEFT'>   <TD>editpaste=1</TD>
   <TD>editproperties=2</TD>
   <TD>editundo=13</TD>
   <TD>exitapp=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>exportbitfile=4</TD>
   <TD>fileprintcmdhandler=1</TD>
   <TD>importports=1</TD>
   <TD>importschematic=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>launchvitis=1</TD>
   <TD>makersbconnection=10</TD>
   <TD>managecompositetargets=22</TD>
   <TD>newexporthardware=20</TD>
</TR><TR ALIGN='LEFT'>   <TD>openblockdesign=24</TD>
   <TD>projectsummary=21</TD>
   <TD>regeneratersblayout=19</TD>
   <TD>reportdrc=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>reportipstatus=1</TD>
   <TD>runbitgen=27</TD>
   <TD>runschematic=31</TD>
   <TD>runsynthesis=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>savedesign=2</TD>
   <TD>saversbdesign=4</TD>
   <TD>showproductguide=1</TD>
   <TD>showproductwebpage=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>showview=12</TD>
   <TD>toolssettings=3</TD>
   <TD>upgradeip=2</TD>
   <TD>validatersbdesign=17</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=1</TD>
   <TD>tclmode=9</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=24</TD>
   <TD>export_simulation_ies=24</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=24</TD>
   <TD>export_simulation_questa=24</TD>
   <TD>export_simulation_riviera=24</TD>
   <TD>export_simulation_vcs=24</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=24</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=0</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=2</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=2</TD>
   <TD>totalsynthesisruns=2</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>and2b1l=1</TD>
    <TD>bscane2=1</TD>
    <TD>bufg=3</TD>
    <TD>carry4=80</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdce=67</TD>
    <TD>fdpe=6</TD>
    <TD>fdre=1774</TD>
    <TD>fdse=69</TD>
</TR><TR ALIGN='LEFT'>    <TD>gnd=308</TD>
    <TD>ibuf=4</TD>
    <TD>lut1=43</TD>
    <TD>lut2=210</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3=424</TD>
    <TD>lut4=384</TD>
    <TD>lut5=429</TD>
    <TD>lut6=747</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv=1</TD>
    <TD>muxf7=109</TD>
    <TD>obuf=2</TD>
    <TD>ramb36e1=16</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramd32=96</TD>
    <TD>rams32=32</TD>
    <TD>srl16e=117</TD>
    <TD>srlc16e=8</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=251</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>and2b1l=1</TD>
    <TD>bscane2=1</TD>
    <TD>bufg=3</TD>
    <TD>carry4=80</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdce=67</TD>
    <TD>fdpe=6</TD>
    <TD>fdre=1774</TD>
    <TD>fdse=69</TD>
</TR><TR ALIGN='LEFT'>    <TD>gnd=308</TD>
    <TD>ibuf=4</TD>
    <TD>lut1=43</TD>
    <TD>lut2=210</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3=424</TD>
    <TD>lut4=384</TD>
    <TD>lut5=349</TD>
    <TD>lut6=667</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6_2=80</TD>
    <TD>mmcme2_adv=1</TD>
    <TD>muxf7=109</TD>
    <TD>obuf=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>ram32m=16</TD>
    <TD>ramb36e1=16</TD>
    <TD>srl16e=117</TD>
    <TD>srlc16e=8</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=251</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>phys_opt_design_post_place</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-aggressive_hold_fix=default::[not_specified]</TD>
    <TD>-bram_register_opt=default::[not_specified]</TD>
    <TD>-clock_opt=default::[not_specified]</TD>
    <TD>-critical_cell_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-critical_pin_opt=default::[not_specified]</TD>
    <TD>-directive=default::[not_specified]</TD>
    <TD>-dsp_register_opt=default::[not_specified]</TD>
    <TD>-effort_level=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fanout_opt=default::[not_specified]</TD>
    <TD>-hold_fix=default::[not_specified]</TD>
    <TD>-insert_negative_edge_ffs=default::[not_specified]</TD>
    <TD>-multi_clock_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-placement_opt=default::[not_specified]</TD>
    <TD>-restruct_opt=default::[not_specified]</TD>
    <TD>-retime=default::[not_specified]</TD>
    <TD>-rewire=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-shift_register_opt=default::[not_specified]</TD>
    <TD>-uram_register_opt=default::[not_specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
    <TD>-vhfn=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-cell_types=default::all</TD>
    <TD>-clocks=default::[not_specified]</TD>
    <TD>-exclude_cells=default::[not_specified]</TD>
    <TD>-include_cells=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bram_ports_augmented=0</TD>
    <TD>bram_ports_newly_gated=0</TD>
    <TD>bram_ports_total=32</TD>
    <TD>flow_state=default</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_augmented=0</TD>
    <TD>slice_registers_newly_gated=0</TD>
    <TD>slice_registers_total=1866</TD>
    <TD>srls_augmented=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>srls_newly_gated=0</TD>
    <TD>srls_total=118</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>IP_Integrator/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bdsource=USER</TD>
    <TD>core_container=NA</TD>
    <TD>da_axi4_cnt=6</TD>
    <TD>da_board_cnt=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>da_mb_cnt=1</TD>
    <TD>iptotal=1</TD>
    <TD>maxhierdepth=1</TD>
    <TD>numblks=24</TD>
</TR><TR ALIGN='LEFT'>    <TD>numhdlrefblks=0</TD>
    <TD>numhierblks=8</TD>
    <TD>numhlsblks=0</TD>
    <TD>numnonxlnxblks=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>numpkgbdblks=0</TD>
    <TD>numreposblks=16</TD>
    <TD>numsysgenblks=0</TD>
    <TD>synth_mode=OOC_per_IP</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=BlockDiagram</TD>
    <TD>x_ipname=system</TD>
    <TD>x_ipvendor=xilinx.com</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipversion=1.00.a</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>MDM/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>x_ipversion=1.00.a</TD>
    <TD>c_addr_size=32</TD>
    <TD>c_avoid_primitives=0</TD>
    <TD>c_bscanid=76547328</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_data_size=32</TD>
    <TD>c_dbg_mem_access=0</TD>
    <TD>c_dbg_reg_access=0</TD>
    <TD>c_debug_interface=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_ext_trig_reset_value=0xF1234</TD>
    <TD>c_family=artix7</TD>
    <TD>c_interconnect=2</TD>
    <TD>c_jtag_chain=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_lmb_protocol=0</TD>
    <TD>c_m_axi_addr_width=32</TD>
    <TD>c_m_axi_data_width=32</TD>
    <TD>c_m_axi_thread_id_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axis_data_width=32</TD>
    <TD>c_m_axis_id_width=7</TD>
    <TD>c_mb_dbg_ports=1</TD>
    <TD>c_s_axi_aclk_freq_hz=100000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_addr_width=4</TD>
    <TD>c_s_axi_data_width=32</TD>
    <TD>c_trace_async_reset=0</TD>
    <TD>c_trace_clk_freq_hz=200000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_trace_clk_out_phase=90</TD>
    <TD>c_trace_data_width=32</TD>
    <TD>c_trace_id=110</TD>
    <TD>c_trace_output=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_trace_protocol=1</TD>
    <TD>c_use_bscan=0</TD>
    <TD>c_use_config_reset=0</TD>
    <TD>c_use_cross_trigger=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_uart=0</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=21</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=mdm</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=3.2</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>MicroBlaze/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_tag_bits=17</TD>
    <TD>c_allow_dcache_wr=1</TD>
    <TD>c_allow_icache_wr=1</TD>
    <TD>c_area_optimized=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_async_interrupt=1</TD>
    <TD>c_async_wakeup=3</TD>
    <TD>c_avoid_primitives=0</TD>
    <TD>c_base_vectors=0x0000000000000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_branch_target_cache_size=0</TD>
    <TD>c_cache_byte_size=8192</TD>
    <TD>c_d_axi=1</TD>
    <TD>c_d_lmb=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_d_lmb_protocol=0</TD>
    <TD>c_daddr_size=32</TD>
    <TD>c_data_size=32</TD>
    <TD>c_dcache_addr_tag=17</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_dcache_always_used=1</TD>
    <TD>c_dcache_baseaddr=0x0000000000000000</TD>
    <TD>c_dcache_byte_size=8192</TD>
    <TD>c_dcache_data_width=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_dcache_force_tag_lutram=0</TD>
    <TD>c_dcache_highaddr=0x000000003fffffff</TD>
    <TD>c_dcache_line_len=4</TD>
    <TD>c_dcache_use_writeback=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_dcache_victims=0</TD>
    <TD>c_debug_counter_width=32</TD>
    <TD>c_debug_enabled=1</TD>
    <TD>c_debug_event_counters=5</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_debug_external_trace=0</TD>
    <TD>c_debug_interface=0</TD>
    <TD>c_debug_latency_counters=1</TD>
    <TD>c_debug_profile_size=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_debug_trace_async_reset=0</TD>
    <TD>c_debug_trace_size=8192</TD>
    <TD>c_div_zero_exception=0</TD>
    <TD>c_dynamic_bus_sizing=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_ecc_use_ce_exception=0</TD>
    <TD>c_edge_is_positive=1</TD>
    <TD>c_endianness=1</TD>
    <TD>c_family=artix7</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_fault_tolerant=0</TD>
    <TD>c_fpu_exception=0</TD>
    <TD>c_freq=100000000</TD>
    <TD>c_fsl_exception=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_fsl_links=0</TD>
    <TD>c_i_axi=0</TD>
    <TD>c_i_lmb=1</TD>
    <TD>c_i_lmb_protocol=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_iaddr_size=32</TD>
    <TD>c_icache_always_used=1</TD>
    <TD>c_icache_baseaddr=0x0000000000000000</TD>
    <TD>c_icache_data_width=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_icache_force_tag_lutram=0</TD>
    <TD>c_icache_highaddr=0x000000003fffffff</TD>
    <TD>c_icache_line_len=4</TD>
    <TD>c_icache_streams=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_icache_victims=0</TD>
    <TD>c_ill_opcode_exception=0</TD>
    <TD>c_imprecise_exceptions=0</TD>
    <TD>c_instance=system_microblaze_0_0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_instr_size=32</TD>
    <TD>c_interconnect=2</TD>
    <TD>c_interrupt_is_edge=0</TD>
    <TD>c_lmb_data_size=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_lockstep_master=0</TD>
    <TD>c_lockstep_slave=0</TD>
    <TD>c_m0_axis_data_width=32</TD>
    <TD>c_m10_axis_data_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m11_axis_data_width=32</TD>
    <TD>c_m12_axis_data_width=32</TD>
    <TD>c_m13_axis_data_width=32</TD>
    <TD>c_m14_axis_data_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m15_axis_data_width=32</TD>
    <TD>c_m1_axis_data_width=32</TD>
    <TD>c_m2_axis_data_width=32</TD>
    <TD>c_m3_axis_data_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m4_axis_data_width=32</TD>
    <TD>c_m5_axis_data_width=32</TD>
    <TD>c_m6_axis_data_width=32</TD>
    <TD>c_m7_axis_data_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m8_axis_data_width=32</TD>
    <TD>c_m9_axis_data_width=32</TD>
    <TD>c_m_axi_d_bus_exception=0</TD>
    <TD>c_m_axi_dc_addr_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_dc_aruser_width=5</TD>
    <TD>c_m_axi_dc_awuser_width=5</TD>
    <TD>c_m_axi_dc_buser_width=1</TD>
    <TD>c_m_axi_dc_data_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_dc_exclusive_access=0</TD>
    <TD>c_m_axi_dc_ruser_width=1</TD>
    <TD>c_m_axi_dc_thread_id_width=1</TD>
    <TD>c_m_axi_dc_user_value=31</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_dc_wuser_width=1</TD>
    <TD>c_m_axi_dp_addr_width=32</TD>
    <TD>c_m_axi_dp_data_width=32</TD>
    <TD>c_m_axi_dp_exclusive_access=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_dp_thread_id_width=1</TD>
    <TD>c_m_axi_i_bus_exception=0</TD>
    <TD>c_m_axi_ic_addr_width=32</TD>
    <TD>c_m_axi_ic_aruser_width=5</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_ic_awuser_width=5</TD>
    <TD>c_m_axi_ic_buser_width=1</TD>
    <TD>c_m_axi_ic_data_width=32</TD>
    <TD>c_m_axi_ic_ruser_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_ic_thread_id_width=1</TD>
    <TD>c_m_axi_ic_user_value=31</TD>
    <TD>c_m_axi_ic_wuser_width=1</TD>
    <TD>c_m_axi_ip_addr_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_ip_data_width=32</TD>
    <TD>c_m_axi_ip_thread_id_width=1</TD>
    <TD>c_mmu_dtlb_size=4</TD>
    <TD>c_mmu_itlb_size=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_mmu_privileged_instr=0</TD>
    <TD>c_mmu_tlb_access=3</TD>
    <TD>c_mmu_zones=16</TD>
    <TD>c_num_sync_ff_clk=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_sync_ff_clk_debug=2</TD>
    <TD>c_num_sync_ff_clk_irq=1</TD>
    <TD>c_num_sync_ff_dbg_clk=1</TD>
    <TD>c_num_sync_ff_dbg_trace_clk=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_number_of_pc_brk=1</TD>
    <TD>c_number_of_rd_addr_brk=0</TD>
    <TD>c_number_of_wr_addr_brk=0</TD>
    <TD>c_opcode_0x0_illegal=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_optimization=0</TD>
    <TD>c_pc_width=32</TD>
    <TD>c_piaddr_size=32</TD>
    <TD>c_pvr=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_pvr_user1=0x00</TD>
    <TD>c_pvr_user2=0x00000000</TD>
    <TD>c_reset_msr=0x00000000</TD>
    <TD>c_s0_axis_data_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s10_axis_data_width=32</TD>
    <TD>c_s11_axis_data_width=32</TD>
    <TD>c_s12_axis_data_width=32</TD>
    <TD>c_s13_axis_data_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s14_axis_data_width=32</TD>
    <TD>c_s15_axis_data_width=32</TD>
    <TD>c_s1_axis_data_width=32</TD>
    <TD>c_s2_axis_data_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s3_axis_data_width=32</TD>
    <TD>c_s4_axis_data_width=32</TD>
    <TD>c_s5_axis_data_width=32</TD>
    <TD>c_s6_axis_data_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s7_axis_data_width=32</TD>
    <TD>c_s8_axis_data_width=32</TD>
    <TD>c_s9_axis_data_width=32</TD>
    <TD>c_sco=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_unaligned_exceptions=0</TD>
    <TD>c_use_barrel=0</TD>
    <TD>c_use_branch_target_cache=0</TD>
    <TD>c_use_config_reset=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_dcache=0</TD>
    <TD>c_use_div=0</TD>
    <TD>c_use_ext_brk=0</TD>
    <TD>c_use_ext_nm_brk=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_extended_fsl_instr=0</TD>
    <TD>c_use_fpu=0</TD>
    <TD>c_use_hw_mul=0</TD>
    <TD>c_use_icache=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_interrupt=1</TD>
    <TD>c_use_mmu=0</TD>
    <TD>c_use_msr_instr=0</TD>
    <TD>c_use_non_secure=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_pcmp_instr=0</TD>
    <TD>c_use_reorder_instr=1</TD>
    <TD>c_use_stack_protection=0</TD>
    <TD>core_container=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>g_template_list=0</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=6</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=microblaze</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=11.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_crossbar_v2_1_25_axi_crossbar/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_axi_addr_width=32</TD>
    <TD>c_axi_aruser_width=1</TD>
    <TD>c_axi_awuser_width=1</TD>
    <TD>c_axi_buser_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_data_width=32</TD>
    <TD>c_axi_id_width=1</TD>
    <TD>c_axi_protocol=2</TD>
    <TD>c_axi_ruser_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_supports_user_signals=0</TD>
    <TD>c_axi_wuser_width=1</TD>
    <TD>c_connectivity_mode=0</TD>
    <TD>c_family=artix7</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_addr_width=0x0000001000000010000000100000001000000010</TD>
    <TD>c_m_axi_base_addr=0x0000000041c000000000000041200000000000004001000000000000406000000000000044a00000</TD>
    <TD>c_m_axi_read_connectivity=0x0000000100000001000000010000000100000001</TD>
    <TD>c_m_axi_read_issuing=0x0000000100000001000000010000000100000001</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_secure=0x0000000000000000000000000000000000000000</TD>
    <TD>c_m_axi_write_connectivity=0x0000000100000001000000010000000100000001</TD>
    <TD>c_m_axi_write_issuing=0x0000000100000001000000010000000100000001</TD>
    <TD>c_num_addr_ranges=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_master_slots=5</TD>
    <TD>c_num_slave_slots=1</TD>
    <TD>c_r_register=1</TD>
    <TD>c_s_axi_arb_priority=0x00000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_base_id=0x00000000</TD>
    <TD>c_s_axi_read_acceptance=0x00000001</TD>
    <TD>c_s_axi_single_thread=0x00000001</TD>
    <TD>c_s_axi_thread_id_width=0x00000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_write_acceptance=0x00000001</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=25</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=axi_crossbar</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=2.1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_gpio/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_all_inputs=1</TD>
    <TD>c_all_inputs_2=0</TD>
    <TD>c_all_outputs=0</TD>
    <TD>c_all_outputs_2=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_dout_default=0x00000000</TD>
    <TD>c_dout_default_2=0x00000000</TD>
    <TD>c_family=artix7</TD>
    <TD>c_gpio2_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_gpio_width=1</TD>
    <TD>c_interrupt_present=1</TD>
    <TD>c_is_dual=0</TD>
    <TD>c_s_axi_addr_width=9</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_data_width=32</TD>
    <TD>c_tri_default=0xFFFFFFFF</TD>
    <TD>c_tri_default_2=0xFFFFFFFF</TD>
    <TD>core_container=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=26</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipname=axi_gpio</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipversion=2.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_intc/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_width=32</TD>
    <TD>c_async_intr=0xFFFFFFF8</TD>
    <TD>c_cascade_master=0</TD>
    <TD>c_disable_synchronizers=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_cascade_mode=0</TD>
    <TD>c_enable_async=0</TD>
    <TD>c_family=artix7</TD>
    <TD>c_has_cie=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_fast=0</TD>
    <TD>c_has_ilr=0</TD>
    <TD>c_has_ipr=1</TD>
    <TD>c_has_ivr=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_sie=1</TD>
    <TD>c_instance=system_axi_intc_0_0</TD>
    <TD>c_irq_active=0x1</TD>
    <TD>c_irq_is_level=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_ivar_reset_value=0x0000000000000010</TD>
    <TD>c_kind_of_edge=0x00000003</TD>
    <TD>c_kind_of_intr=0x00000002</TD>
    <TD>c_kind_of_lvl=0xFFFFFFFF</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_mb_clk_not_connected=1</TD>
    <TD>c_num_intr_inputs=3</TD>
    <TD>c_num_sw_intr=0</TD>
    <TD>c_num_sync_ff=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_addr_width=9</TD>
    <TD>c_s_axi_data_width=32</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipcorerevision=15</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=axi_intc</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipproduct=Vivado 2021.1</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=4.1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_timer/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_count_width=32</TD>
    <TD>c_family=artix7</TD>
    <TD>c_gen0_assert=1</TD>
    <TD>c_gen1_assert=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_one_timer_only=1</TD>
    <TD>c_s_axi_addr_width=5</TD>
    <TD>c_s_axi_data_width=32</TD>
    <TD>c_trig0_assert=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_trig1_assert=1</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=26</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=axi_timer</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=2.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_uartlite/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_baudrate=115200</TD>
    <TD>c_data_bits=8</TD>
    <TD>c_family=artix7</TD>
    <TD>c_odd_parity=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_aclk_freq_hz=100000000</TD>
    <TD>c_s_axi_addr_width=4</TD>
    <TD>c_s_axi_data_width=32</TD>
    <TD>c_use_parity=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=28</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=axi_uartlite</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=2.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>blk_mem_gen_v8_4_4/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addra_width=32</TD>
    <TD>c_addrb_width=32</TD>
    <TD>c_algorithm=1</TD>
    <TD>c_axi_id_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_slave_type=0</TD>
    <TD>c_axi_type=1</TD>
    <TD>c_byte_size=8</TD>
    <TD>c_common_clk=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_count_18k_bram=0</TD>
    <TD>c_count_36k_bram=16</TD>
    <TD>c_ctrl_ecc_algo=NONE</TD>
    <TD>c_default_data=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_disable_warn_bhv_coll=0</TD>
    <TD>c_disable_warn_bhv_range=0</TD>
    <TD>c_elaboration_dir=./</TD>
    <TD>c_en_deepsleep_pin=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_ecc_pipe=0</TD>
    <TD>c_en_rdaddra_chg=0</TD>
    <TD>c_en_rdaddrb_chg=0</TD>
    <TD>c_en_safety_ckt=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_shutdown_pin=0</TD>
    <TD>c_en_sleep_pin=0</TD>
    <TD>c_enable_32bit_address=1</TD>
    <TD>c_est_power_summary=Estimated Power for IP     _     20.388 mW</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=artix7</TD>
    <TD>c_has_axi_id=0</TD>
    <TD>c_has_ena=1</TD>
    <TD>c_has_enb=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_injecterr=0</TD>
    <TD>c_has_mem_output_regs_a=0</TD>
    <TD>c_has_mem_output_regs_b=0</TD>
    <TD>c_has_mux_output_regs_a=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_mux_output_regs_b=0</TD>
    <TD>c_has_regcea=0</TD>
    <TD>c_has_regceb=0</TD>
    <TD>c_has_rsta=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_rstb=1</TD>
    <TD>c_has_softecc_input_regs_a=0</TD>
    <TD>c_has_softecc_output_regs_b=0</TD>
    <TD>c_init_file=system_lmb_bram_0.mem</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_init_file_name=no_coe_file_loaded</TD>
    <TD>c_inita_val=0</TD>
    <TD>c_initb_val=0</TD>
    <TD>c_interface_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_load_init_file=0</TD>
    <TD>c_mem_type=2</TD>
    <TD>c_mux_pipeline_stages=0</TD>
    <TD>c_prim_type=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_read_depth_a=16384</TD>
    <TD>c_read_depth_b=16384</TD>
    <TD>c_read_latency_a=1</TD>
    <TD>c_read_latency_b=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_read_width_a=32</TD>
    <TD>c_read_width_b=32</TD>
    <TD>c_rst_priority_a=CE</TD>
    <TD>c_rst_priority_b=CE</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rstram_a=0</TD>
    <TD>c_rstram_b=0</TD>
    <TD>c_sim_collision_check=ALL</TD>
    <TD>c_use_bram_block=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_byte_wea=1</TD>
    <TD>c_use_byte_web=1</TD>
    <TD>c_use_default_data=0</TD>
    <TD>c_use_ecc=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_softecc=0</TD>
    <TD>c_use_uram=0</TD>
    <TD>c_wea_width=4</TD>
    <TD>c_web_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_write_depth_a=16384</TD>
    <TD>c_write_depth_b=16384</TD>
    <TD>c_write_mode_a=WRITE_FIRST</TD>
    <TD>c_write_mode_b=WRITE_FIRST</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_write_width_a=32</TD>
    <TD>c_write_width_b=32</TD>
    <TD>c_xdevicefamily=artix7</TD>
    <TD>core_container=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=4</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipname=blk_mem_gen</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipversion=8.4</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>breath_led_ip_v1_0/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_s01_axi_addr_width=4</TD>
    <TD>c_s01_axi_data_width=32</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>start_freq_step=10</TD>
    <TD>x_ipcorerevision=4</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=user</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipname=breath_led_ip</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v6_0_8_0_0/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>clkin1_period=20.000</TD>
    <TD>clkin2_period=10.0</TD>
    <TD>clock_mgr_type=NA</TD>
    <TD>component_name=system_clk_wiz_1_0</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>enable_axi=0</TD>
    <TD>feedback_source=FDBK_AUTO</TD>
    <TD>feedback_type=SINGLE</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>manual_override=false</TD>
    <TD>num_out_clk=1</TD>
    <TD>primitive=MMCM</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_dyn_phase_shift=false</TD>
    <TD>use_dyn_reconfig=false</TD>
    <TD>use_inclk_stopped=false</TD>
    <TD>use_inclk_switchover=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_locked=true</TD>
    <TD>use_max_i_jitter=false</TD>
    <TD>use_min_o_jitter=false</TD>
    <TD>use_phase_alignment=true</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_power_down=false</TD>
    <TD>use_reset=true</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>lmb_bram_if_cntlr/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_baseaddr=0x0000000000000000</TD>
    <TD>c_bram_awidth=32</TD>
    <TD>c_ce_counter_width=0</TD>
    <TD>c_ce_failing_registers=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_ecc=0</TD>
    <TD>c_ecc_onoff_register=0</TD>
    <TD>c_ecc_onoff_reset_value=1</TD>
    <TD>c_ecc_status_registers=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=artix7</TD>
    <TD>c_fault_inject=0</TD>
    <TD>c_highaddr=0x000000000000FFFF</TD>
    <TD>c_interconnect=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_lmb_awidth=32</TD>
    <TD>c_lmb_dwidth=32</TD>
    <TD>c_lmb_protocol=0</TD>
    <TD>c_mask=0x0000000040000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_mask1=0x0000000000800000</TD>
    <TD>c_mask2=0x0000000000800000</TD>
    <TD>c_mask3=0x0000000000800000</TD>
    <TD>c_num_lmb=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_ctrl_addr_width=32</TD>
    <TD>c_s_axi_ctrl_data_width=32</TD>
    <TD>c_ue_failing_registers=0</TD>
    <TD>c_write_access=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=19</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=lmb_bram_if_cntlr</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=4.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>lmb_bram_if_cntlr/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_baseaddr=0x0000000000000000</TD>
    <TD>c_bram_awidth=32</TD>
    <TD>c_ce_counter_width=0</TD>
    <TD>c_ce_failing_registers=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_ecc=0</TD>
    <TD>c_ecc_onoff_register=0</TD>
    <TD>c_ecc_onoff_reset_value=1</TD>
    <TD>c_ecc_status_registers=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=artix7</TD>
    <TD>c_fault_inject=0</TD>
    <TD>c_highaddr=0x000000000000FFFF</TD>
    <TD>c_interconnect=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_lmb_awidth=32</TD>
    <TD>c_lmb_dwidth=32</TD>
    <TD>c_lmb_protocol=0</TD>
    <TD>c_mask=0x0000000000000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_mask1=0x0000000000800000</TD>
    <TD>c_mask2=0x0000000000800000</TD>
    <TD>c_mask3=0x0000000000800000</TD>
    <TD>c_num_lmb=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_ctrl_addr_width=32</TD>
    <TD>c_s_axi_ctrl_data_width=32</TD>
    <TD>c_ue_failing_registers=0</TD>
    <TD>c_write_access=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=19</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=lmb_bram_if_cntlr</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=4.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>lmb_v10/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_ext_reset_high=1</TD>
    <TD>c_lmb_awidth=32</TD>
    <TD>c_lmb_dwidth=32</TD>
    <TD>c_lmb_num_slaves=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_lmb_protocol=0</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=2</TD>
    <TD>x_ipcorerevision=11</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=lmb_v10</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=3.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>proc_sys_reset/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aux_reset_high=0</TD>
    <TD>c_aux_rst_width=4</TD>
    <TD>c_ext_reset_high=0</TD>
    <TD>c_ext_rst_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=artix7</TD>
    <TD>c_num_bus_rst=1</TD>
    <TD>c_num_interconnect_aresetn=1</TD>
    <TD>c_num_perp_aresetn=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_perp_rst=1</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=13</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=proc_sys_reset</TD>
    <TD>x_ipproduct=Vivado 2021.1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=5.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xlconcat_v2_1_4_xlconcat/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>dout_width=3</TD>
    <TD>in0_width=1</TD>
    <TD>in100_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in101_width=1</TD>
    <TD>in102_width=1</TD>
    <TD>in103_width=1</TD>
    <TD>in104_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in105_width=1</TD>
    <TD>in106_width=1</TD>
    <TD>in107_width=1</TD>
    <TD>in108_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in109_width=1</TD>
    <TD>in10_width=1</TD>
    <TD>in110_width=1</TD>
    <TD>in111_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in112_width=1</TD>
    <TD>in113_width=1</TD>
    <TD>in114_width=1</TD>
    <TD>in115_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in116_width=1</TD>
    <TD>in117_width=1</TD>
    <TD>in118_width=1</TD>
    <TD>in119_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in11_width=1</TD>
    <TD>in120_width=1</TD>
    <TD>in121_width=1</TD>
    <TD>in122_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in123_width=1</TD>
    <TD>in124_width=1</TD>
    <TD>in125_width=1</TD>
    <TD>in126_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in127_width=1</TD>
    <TD>in12_width=1</TD>
    <TD>in13_width=1</TD>
    <TD>in14_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in15_width=1</TD>
    <TD>in16_width=1</TD>
    <TD>in17_width=1</TD>
    <TD>in18_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in19_width=1</TD>
    <TD>in1_width=1</TD>
    <TD>in20_width=1</TD>
    <TD>in21_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in22_width=1</TD>
    <TD>in23_width=1</TD>
    <TD>in24_width=1</TD>
    <TD>in25_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in26_width=1</TD>
    <TD>in27_width=1</TD>
    <TD>in28_width=1</TD>
    <TD>in29_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in2_width=1</TD>
    <TD>in30_width=1</TD>
    <TD>in31_width=1</TD>
    <TD>in32_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in33_width=1</TD>
    <TD>in34_width=1</TD>
    <TD>in35_width=1</TD>
    <TD>in36_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in37_width=1</TD>
    <TD>in38_width=1</TD>
    <TD>in39_width=1</TD>
    <TD>in3_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in40_width=1</TD>
    <TD>in41_width=1</TD>
    <TD>in42_width=1</TD>
    <TD>in43_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in44_width=1</TD>
    <TD>in45_width=1</TD>
    <TD>in46_width=1</TD>
    <TD>in47_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in48_width=1</TD>
    <TD>in49_width=1</TD>
    <TD>in4_width=1</TD>
    <TD>in50_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in51_width=1</TD>
    <TD>in52_width=1</TD>
    <TD>in53_width=1</TD>
    <TD>in54_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in55_width=1</TD>
    <TD>in56_width=1</TD>
    <TD>in57_width=1</TD>
    <TD>in58_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in59_width=1</TD>
    <TD>in5_width=1</TD>
    <TD>in60_width=1</TD>
    <TD>in61_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in62_width=1</TD>
    <TD>in63_width=1</TD>
    <TD>in64_width=1</TD>
    <TD>in65_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in66_width=1</TD>
    <TD>in67_width=1</TD>
    <TD>in68_width=1</TD>
    <TD>in69_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in6_width=1</TD>
    <TD>in70_width=1</TD>
    <TD>in71_width=1</TD>
    <TD>in72_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in73_width=1</TD>
    <TD>in74_width=1</TD>
    <TD>in75_width=1</TD>
    <TD>in76_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in77_width=1</TD>
    <TD>in78_width=1</TD>
    <TD>in79_width=1</TD>
    <TD>in7_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in80_width=1</TD>
    <TD>in81_width=1</TD>
    <TD>in82_width=1</TD>
    <TD>in83_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in84_width=1</TD>
    <TD>in85_width=1</TD>
    <TD>in86_width=1</TD>
    <TD>in87_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in88_width=1</TD>
    <TD>in89_width=1</TD>
    <TD>in8_width=1</TD>
    <TD>in90_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in91_width=1</TD>
    <TD>in92_width=1</TD>
    <TD>in93_width=1</TD>
    <TD>in94_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in95_width=1</TD>
    <TD>in96_width=1</TD>
    <TD>in97_width=1</TD>
    <TD>in98_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in99_width=1</TD>
    <TD>in9_width=1</TD>
    <TD>iptotal=1</TD>
    <TD>num_ports=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipcorerevision=4</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=xlconcat</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipproduct=Vivado 2021.1</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=2.1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_design_analysis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-bounding_boxes=default::[not_specified]</TD>
    <TD>-cells=default::[not_specified]</TD>
    <TD>-complexity=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-congestion=default::[not_specified]</TD>
    <TD>-end_point_clocks=default::[not_specified]</TD>
    <TD>-extend=default::[not_specified]</TD>
    <TD>-extract_metrics=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-file=default::[not_specified]</TD>
    <TD>-full_logical_pin=default::[not_specified]</TD>
    <TD>-hierarchical_depth=default::[not_specified]</TD>
    <TD>-hold=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-logic_level_dist_paths=default::[not_specified]</TD>
    <TD>-logic_level_distribution=default::[not_specified]</TD>
    <TD>-logic_levels=default::[not_specified]</TD>
    <TD>-max_level=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_paths=default::[not_specified]</TD>
    <TD>-min_congestion_level=default::5</TD>
    <TD>-min_level=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_header=default::[not_specified]</TD>
    <TD>-of_timing_paths=default::[not_specified]</TD>
    <TD>-pploc_distance=default::[not_specified]</TD>
    <TD>-qor_summary=[specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-quiet=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-return_timing_paths=default::[not_specified]</TD>
    <TD>-routed_vs_estimated=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-routes=default::[not_specified]</TD>
    <TD>-setup=default::[not_specified]</TD>
    <TD>-show_all_congestion_windows=default::false</TD>
    <TD>-suggestion=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-timing=default::[not_specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>runtime=0.138 secs</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage_count</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>qor_summary=4</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-internal=default::[not_specified]</TD>
    <TD>-internal_only=default::[not_specified]</TD>
    <TD>-max_msgs_per_check=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_waivers=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-ruledecks=default::[not_specified]</TD>
    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>cfgbvs-1=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-merge_exceptions =default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-return_string=default::[not_specified]</TD>
    <TD>-slack_lesser_than=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>lutar-1=1</TD>
    <TD>timing-9=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-advisory=default::[not_specified]</TD>
    <TD>-append=default::[not_specified]</TD>
    <TD>-file=[specified]</TD>
    <TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'>    <TD>-hier=default::power</TD>
    <TD>-hierarchical_depth=default::4</TD>
    <TD>-l=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_propagation=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-rpx=[specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-vid=default::[not_specified]</TD>
    <TD>-xpe=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>airflow=250 (LFM)</TD>
    <TD>ambient_temp=25.0 (C)</TD>
    <TD>bi-dir_toggle=12.500000</TD>
    <TD>bidir_output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>board_layers=12to15 (12 to 15 Layers)</TD>
    <TD>board_selection=medium (10&quot;x10&quot;)</TD>
    <TD>bram=0.003436</TD>
    <TD>clocks=0.010189</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_clock_activity=High</TD>
    <TD>confidence_level_design_state=High</TD>
    <TD>confidence_level_device_models=High</TD>
    <TD>confidence_level_internal_activity=Medium</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_io_activity=Medium</TD>
    <TD>confidence_level_overall=Medium</TD>
    <TD>customer=TBD</TD>
    <TD>customer_class=TBD</TD>
</TR><TR ALIGN='LEFT'>    <TD>devstatic=0.139515</TD>
    <TD>die=xc7a200tfbg484-2</TD>
    <TD>dsp_output_toggle=12.500000</TD>
    <TD>dynamic=0.128993</TD>
</TR><TR ALIGN='LEFT'>    <TD>effective_thetaja=2.47</TD>
    <TD>enable_probability=0.990000</TD>
    <TD>family=artix7</TD>
    <TD>ff_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>flow_state=routed</TD>
    <TD>heatsink=medium (Medium Profile)</TD>
    <TD>i/o=0.000188</TD>
    <TD>input_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>junction_temp=25.7 (C)</TD>
    <TD>logic=0.004324</TD>
    <TD>mgtavcc_dynamic_current=0.000000</TD>
    <TD>mgtavcc_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavcc_total_current=0.000000</TD>
    <TD>mgtavcc_voltage=1.000000</TD>
    <TD>mgtavtt_dynamic_current=0.000000</TD>
    <TD>mgtavtt_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavtt_total_current=0.000000</TD>
    <TD>mgtavtt_voltage=1.200000</TD>
    <TD>mmcm=0.105339</TD>
    <TD>netlist_net_matched=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>off-chip_power=0.000000</TD>
    <TD>on-chip_power=0.268508</TD>
    <TD>output_enable=1.000000</TD>
    <TD>output_load=5.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>output_toggle=12.500000</TD>
    <TD>package=fbg484</TD>
    <TD>pct_clock_constrained=3.000000</TD>
    <TD>pct_inputs_defined=25</TD>
</TR><TR ALIGN='LEFT'>    <TD>platform=nt64</TD>
    <TD>process=typical</TD>
    <TD>ram_enable=50.000000</TD>
    <TD>ram_write=50.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>read_saif=False</TD>
    <TD>set/reset_probability=0.000000</TD>
    <TD>signal_rate=False</TD>
    <TD>signals=0.005518</TD>
</TR><TR ALIGN='LEFT'>    <TD>simulation_file=None</TD>
    <TD>speedgrade=-2</TD>
    <TD>static_prob=False</TD>
    <TD>temp_grade=commercial</TD>
</TR><TR ALIGN='LEFT'>    <TD>thetajb=4.8 (C/W)</TD>
    <TD>thetasa=4.2 (C/W)</TD>
    <TD>toggle_rate=False</TD>
    <TD>user_board_temp=25.0 (C)</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_effective_thetaja=2.47</TD>
    <TD>user_junc_temp=25.7 (C)</TD>
    <TD>user_thetajb=4.8 (C/W)</TD>
    <TD>user_thetasa=4.2 (C/W)</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccadc_dynamic_current=0.000000</TD>
    <TD>vccadc_static_current=0.020000</TD>
    <TD>vccadc_total_current=0.020000</TD>
    <TD>vccadc_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_dynamic_current=0.058352</TD>
    <TD>vccaux_io_dynamic_current=0.000000</TD>
    <TD>vccaux_io_static_current=0.000000</TD>
    <TD>vccaux_io_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_io_voltage=1.800000</TD>
    <TD>vccaux_static_current=0.030539</TD>
    <TD>vccaux_total_current=0.088891</TD>
    <TD>vccaux_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccbram_dynamic_current=0.000295</TD>
    <TD>vccbram_static_current=0.001109</TD>
    <TD>vccbram_total_current=0.001404</TD>
    <TD>vccbram_voltage=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccint_dynamic_current=0.023525</TD>
    <TD>vccint_static_current=0.030936</TD>
    <TD>vccint_total_current=0.054461</TD>
    <TD>vccint_voltage=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco12_dynamic_current=0.000000</TD>
    <TD>vcco12_static_current=0.000000</TD>
    <TD>vcco12_total_current=0.000000</TD>
    <TD>vcco12_voltage=1.200000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco135_dynamic_current=0.000000</TD>
    <TD>vcco135_static_current=0.000000</TD>
    <TD>vcco135_total_current=0.000000</TD>
    <TD>vcco135_voltage=1.350000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco15_dynamic_current=0.000000</TD>
    <TD>vcco15_static_current=0.000000</TD>
    <TD>vcco15_total_current=0.000000</TD>
    <TD>vcco15_voltage=1.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco18_dynamic_current=0.000000</TD>
    <TD>vcco18_static_current=0.000000</TD>
    <TD>vcco18_total_current=0.000000</TD>
    <TD>vcco18_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco25_dynamic_current=0.000000</TD>
    <TD>vcco25_static_current=0.000000</TD>
    <TD>vcco25_total_current=0.000000</TD>
    <TD>vcco25_voltage=2.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco33_dynamic_current=0.000042</TD>
    <TD>vcco33_static_current=0.005000</TD>
    <TD>vcco33_total_current=0.005042</TD>
    <TD>vcco33_voltage=3.300000</TD>
</TR><TR ALIGN='LEFT'>    <TD>version=2021.1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_prohibited=0</TD>
    <TD>bufgctrl_used=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufgctrl_util_percentage=12.50</TD>
    <TD>bufhce_available=120</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
    <TD>bufio_available=40</TD>
    <TD>bufio_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_prohibited=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
    <TD>bufmrce_available=20</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_prohibited=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=40</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_prohibited=0</TD>
    <TD>bufr_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_util_percentage=0.00</TD>
    <TD>mmcme2_adv_available=10</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_used=1</TD>
    <TD>mmcme2_adv_util_percentage=10.00</TD>
    <TD>plle2_adv_available=10</TD>
    <TD>plle2_adv_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_prohibited=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=740</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_prohibited=0</TD>
    <TD>dsps_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=0</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=365</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_prohibited=0</TD>
    <TD>block_ram_tile_used=16</TD>
</TR><TR ALIGN='LEFT'>    <TD>block_ram_tile_util_percentage=4.38</TD>
    <TD>ramb18_available=730</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_used=0</TD>
    <TD>ramb18_util_percentage=0.00</TD>
    <TD>ramb36_fifo_available=365</TD>
    <TD>ramb36_fifo_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_prohibited=0</TD>
    <TD>ramb36_fifo_used=16</TD>
    <TD>ramb36_fifo_util_percentage=4.38</TD>
    <TD>ramb36e1_only_used=16</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>and2b1l_functional_category=Others</TD>
    <TD>and2b1l_used=1</TD>
    <TD>bscane2_functional_category=Others</TD>
    <TD>bscane2_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=4</TD>
    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=80</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdce_functional_category=Flop &amp; Latch</TD>
    <TD>fdce_used=67</TD>
    <TD>fdpe_functional_category=Flop &amp; Latch</TD>
    <TD>fdpe_used=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=1726</TD>
    <TD>fdse_functional_category=Flop &amp; Latch</TD>
    <TD>fdse_used=67</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=4</TD>
    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=24</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=202</TD>
    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=406</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=351</TD>
    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=450</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=697</TD>
    <TD>mmcme2_adv_functional_category=Clock</TD>
    <TD>mmcme2_adv_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf7_functional_category=MuxFx</TD>
    <TD>muxf7_used=109</TD>
    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36e1_functional_category=Block Memory</TD>
    <TD>ramb36e1_used=16</TD>
    <TD>ramd32_functional_category=Distributed Memory</TD>
    <TD>ramd32_used=96</TD>
</TR><TR ALIGN='LEFT'>    <TD>rams32_functional_category=Distributed Memory</TD>
    <TD>rams32_used=32</TD>
    <TD>srl16e_functional_category=Distributed Memory</TD>
    <TD>srl16e_used=111</TD>
</TR><TR ALIGN='LEFT'>    <TD>srlc16e_functional_category=Distributed Memory</TD>
    <TD>srlc16e_used=7</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=66900</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_prohibited=400</TD>
    <TD>f7_muxes_used=109</TD>
</TR><TR ALIGN='LEFT'>    <TD>f7_muxes_util_percentage=0.16</TD>
    <TD>f8_muxes_available=33450</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_prohibited=200</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_used=0</TD>
    <TD>f8_muxes_util_percentage=0.00</TD>
    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=64</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=133800</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_prohibited=800</TD>
    <TD>lut_as_logic_used=1748</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_util_percentage=1.31</TD>
    <TD>lut_as_memory_available=46200</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=138</TD>
    <TD>lut_as_memory_util_percentage=0.30</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=74</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_and_or_available=269200</TD>
    <TD>register_as_and_or_fixed=0</TD>
    <TD>register_as_and_or_prohibited=0</TD>
    <TD>register_as_and_or_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_and_or_util_percentage=&lt;0.01</TD>
    <TD>register_as_flip_flop_available=269200</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_used=1866</TD>
    <TD>register_as_flip_flop_util_percentage=0.69</TD>
    <TD>register_as_latch_available=269200</TD>
    <TD>register_as_latch_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_prohibited=0</TD>
    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
    <TD>slice_luts_available=133800</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_prohibited=800</TD>
    <TD>slice_luts_used=1886</TD>
    <TD>slice_luts_util_percentage=1.41</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=269200</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_prohibited=0</TD>
    <TD>slice_registers_used=1867</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_util_percentage=0.69</TD>
    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=64</TD>
    <TD>lut_as_logic_available=133800</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_prohibited=800</TD>
    <TD>lut_as_logic_used=1748</TD>
    <TD>lut_as_logic_util_percentage=1.31</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=46200</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_prohibited=0</TD>
    <TD>lut_as_memory_used=138</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_util_percentage=0.30</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=74</TD>
    <TD>lut_in_front_of_the_register_is_unused_available=74</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_in_front_of_the_register_is_unused_fixed=74</TD>
    <TD>lut_in_front_of_the_register_is_unused_prohibited=74</TD>
    <TD>lut_in_front_of_the_register_is_unused_used=552</TD>
    <TD>lut_in_front_of_the_register_is_used_available=552</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_in_front_of_the_register_is_used_fixed=552</TD>
    <TD>lut_in_front_of_the_register_is_used_prohibited=552</TD>
    <TD>lut_in_front_of_the_register_is_used_used=349</TD>
    <TD>register_driven_from_outside_the_slice_fixed=349</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_driven_from_outside_the_slice_used=901</TD>
    <TD>register_driven_from_within_the_slice_fixed=901</TD>
    <TD>register_driven_from_within_the_slice_used=966</TD>
    <TD>slice_available=33450</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_fixed=0</TD>
    <TD>slice_prohibited=200</TD>
    <TD>slice_registers_available=269200</TD>
    <TD>slice_registers_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_prohibited=0</TD>
    <TD>slice_registers_used=1867</TD>
    <TD>slice_registers_util_percentage=0.69</TD>
    <TD>slice_used=705</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_util_percentage=2.11</TD>
    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=461</TD>
    <TD>slicem_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicem_used=244</TD>
    <TD>unique_control_sets_available=33450</TD>
    <TD>unique_control_sets_fixed=33450</TD>
    <TD>unique_control_sets_prohibited=200</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_used=103</TD>
    <TD>unique_control_sets_util_percentage=0.31</TD>
    <TD>using_o5_and_o6_available=0.31</TD>
    <TD>using_o5_and_o6_fixed=0.31</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_prohibited=0.31</TD>
    <TD>using_o5_and_o6_used=44</TD>
    <TD>using_o5_output_only_available=44</TD>
    <TD>using_o5_output_only_fixed=44</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_output_only_prohibited=44</TD>
    <TD>using_o5_output_only_used=8</TD>
    <TD>using_o6_output_only_available=8</TD>
    <TD>using_o6_output_only_fixed=8</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_prohibited=8</TD>
    <TD>using_o6_output_only_used=22</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_prohibited=0</TD>
    <TD>bscane2_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>bscane2_util_percentage=25.00</TD>
    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_prohibited=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
    <TD>efuse_usr_available=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_prohibited=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_prohibited=0</TD>
    <TD>frame_ecce2_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_util_percentage=0.00</TD>
    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
    <TD>pcie_2_1_available=1</TD>
    <TD>pcie_2_1_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcie_2_1_prohibited=0</TD>
    <TD>pcie_2_1_used=0</TD>
    <TD>pcie_2_1_util_percentage=0.00</TD>
    <TD>startupe2_available=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_prohibited=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_prohibited=0</TD>
    <TD>xadc_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-debug_log=default::[not_specified]</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
</TR><TR ALIGN='LEFT'>    <TD>-flatten_hierarchy=default::rebuilt</TD>
    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-include_dirs=default::[not_specified]</TD>
    <TD>-incremental=default::[not_specified]</TD>
    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-lint=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
    <TD>-max_uram=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_lc=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-os=default::[not_specified]</TD>
    <TD>-part=xc7a200tfbg484-2</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=system_wrapper</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:28s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=51.156MB</TD>
    <TD>memory_peak=1337.086MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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